Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105 (also referred to as “MTJ stack”), a transistor 101, a bit line 102 and a word line 103. The MTJ stack is formed, for example, from a pinned layer 124 and a free layer 120, each of which can hold a magnetic moment or polarization, separated by an insulating tunneling barrier layer 122. There is conventionally an anti-ferromagnetic (AFM) layer and a cap layer (not shown) in the MTJ stack. The AFM layer is used to pin the magnetic moment of the pinned layer. The cap layer is used as a buffer layer between the MTJ and metal interconnects. The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read the bit cell 100, as is known. The STT-MRAM bit cell 100 also includes a source line 104, a sense amplifier 108, read/write circuitry 106 and a bit line reference 107. Those skilled in the art will appreciate the operation and construction of the memory cell 100 as known in the art.
MRAM cells are commonly integrated with various other logic gates and electronic components such as transistors, capacitors, metal wires, etc., in the development of memory devices. Accordingly, it is desirable that the process of manufacturing MTJ elements remains compatible with the constraints inherent to manufacture of integrated circuits. However, it is well known that semiconductor technology scaling is not uniform across all components involved in the manufacture of integrated circuits. For example, metal wire width and sizes of Vertical Interconnect Access (commonly known as “via”) are scale by about 70% from one generation to the next. However, interlayer metal dielectric (IMD) thickness scaling is much smaller than 70% because diffusion cap layers cannot scale that fast. Therefore, the capacitors scale down at a much slower rate. More particularly, scaling down of height of MTJ cells is even slower and in comparison to other electronic components in integrated circuits, the scaling is almost non-existent in the current state of the art.
The disproportionate rate of scaling in different components gives rise to various challenges in the design and manufacture of integrated circuits. With regard to circuits involving the use of MRAM cells, there are numerous problems associated with integration of rapidly shrinking electronic components with relatively unchanging MRAM sizes. For purposes of this discussion, electronic components such as transistors, metal wires, capacitors, vias, etc, which are not a part of the MRAM cell are generally referred to as “logic elements”; and the process of their integration is referred to as “logic process”. The integration process of MRAM elements is generally referred to as “MRAM process”. It is desirable for the MRAM process to be compatible with the related logic process. Therefore, it would be beneficial to embed the MRAM process into the logic process flow.
A cross-sectional view of a memory device including at least one MRAM cell is illustrated in FIG. 2. Elements of a particular device layer “x”, the layer below, “x−1”, and the layer above, “x+1”, are shown. Both logic elements and MRAM components are illustrated in juxtaposition. The logic elements are generally represented by metal wires M′x/Mx and M′x−1/Mx−1 in layers x, and x−1 respectively; via V′x in layer x; insulating layers Cap1x and Cap2x in layer x, and Cap1x+1 and Cap2x+1 in layer x+1. The MRAM components comprise an MTJ stack (such as MTJ105) formed between top electrode (TE) and bottom electrode (BE); metal wires Mx and Mx−1 (constituting, for example, bit line 102 and source line 104) in layers x and x−1 respectively; inter-metal-dielectric layers IMDx and IMDx−1; via Vx in layer x; and insulating layers Cap1x and Cap2x in layer x, and Cap1x+1 and Cap2x+1 in layer x+1. The insulating cap layers are used as a diffusion barrier layer for the metal wires. The various cap layers may be formed from known insulators, for example, from materials such as SiC, SiN film, and the like. Further, it will be appreciated that conventional materials and processing techniques can be used for the various logic, metal, and IMD elements discussed herein.
With continuing reference to FIG. 2, L2 represents the height of the MRAM cell including the bottom electrode BE, MTJ stack, and top electrode TE. In general, the vertical distance between metal wires in adjacent layers is the maximum space available for forming the MRAM cell. Accordingly, the MRAM cell in layer x must be contained within metal wires Mx and Mx−1. However, as shown in FIG. 2, this available vertical space is also shared by elements such as vias, insulating layers, and common IMD layer. Accounting for the vertical space consumed by these elements, L1 represents the effective vertical space between the metal layers that is available for the MRAM cell. Trends in technology scaling reveal that the vertical space between layers is rapidly shrinking. However, as previously noted, the thickness of cap layer is not scaling down at the same rate and the scaling rate is slower. Further, as illustrated, a bi-layer insulating structure may be utilized in order to balance mechanical stress introduced by the bottom electrode BE, imposing further restrictions on the available space.
As a result, the available vertical space for formation of the MRAM cell, L1, is less than the actual height, L2, of the MRAM cell. Therefore there is an overlap where the MRAM cell intrudes into the metal wire Mx, as shown. The intrusion creates several problems. Firstly, the danger of a short-circuit is created between the metal Mx and the sidewalls and/or the tunneling barrier layer of the MTJ stack. The issue may be exacerbated in devices with a high density of MRAM cells, because the thin IMD filling between multiple MRAM cells may be insufficient to protect the sidewalls of the cells during etching and metallization processes. Moreover, the introduction of bi-layer insulating caps elevates the vertical position of the MTJ element, thereby increasing the intrusion with metal Mx.